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One of the most important parts of the CPU design! All the units
operate asynchronously, and can be operating in parallel. Yet
they all ultimately want to write the results of their
computation to the register file using the internal bus. The
result arbitration circuit helps to decide who can use the bus
at what time.
There are 5 units which may need to write
back results. In addition the instruction issue unit will
require the bus to load source data from the register file
to the units. I therefore arrange a stack of 5 flip flops.
There is a "result phase" during which the instruction issue unit
allows results to be written. In this phase, each of the
5 possible units are checked and in turn allowed to write
their results if they need to.
