![]() |
Page 38 | Page 40 | ![]() |
This is a set of 74LS374 octal D-type latches, 40-bits wide, one
bank for the input and on e for the output. Using these
the host Z80 can send data to and from the CPU.
When the CPU
executes an IN instruction, a Z80 interrupt gets generated. The
IOU is then marked as busy on the unit scoreboard until the
Z80 has loaded all 5 8-bit registers, so a complete 40-bit CPU
word is ready. Only then does the IOU send a "finish" signal to
the Result Arbitration circuit.
When the CPU executes an OUT instruction, a Z80 interrupt is also
generated. The IOU busy scoreboard bit remains set until the
Z80 has read all the 5 8-bit chunks of the 40-bit word.