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Complete design for the multiplier.
When multiplying two
floating point numbers together, it isn't necessary to align them
first. Just multiply them, and take the most significant bits
of the result. Meanwhile, add the exponents. Post-multplication
normalisation will only ever result in a shift of 1 bit, so
I don't need a full barrel shifter, instead I just have a multiplexer
with its inputs both connected to the multiplcation result
but displaced by one bit.
This unit can also multiply integers. In this case, the product
is twice as wide as the operands. I decide that I must store this
extra result word somewhere, it would be a shame to waste it. Register 15 seems
like the ideal place. Previously I had specified register 15 to
be the Program Counter. However, the Program Counter does not
need to be accessible for read or write by the executing program,
it is entirely under the control of the instruction decode
related units. So I hide it from the register bank and use
register 15 for the least significant word of the result. The
most significant word goes to the specified result register.
The multiply circuit itself is not shown here, it's just drawn
as a block with the MULT caption. I intend to use a fast parallel
multiplier, I had some papers from the libary about how to build
one of those, but unfortunately it requires a large number of
chips. I decide not to draw it here, but just to consider it as
a functional block: give it two numbers and it will return
the product some time later.
I also make the controverial decision to pipeline this unit, since
it has a parallel multiplier. However, I don't pipeline it in
the conventional way, with a register between each processing
stage and clock the results along the pipeline. Instead I use
ripple-through (wave) pipelining. Just shove the inputs in one
after the other, wait the right amount of time, and take
the output. Believe it or not, wave-pipelined parallel multipliers
have been built in practice. Whether or not I could ever get it
working is debateable.
