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Which now also shows register 15 as the multiplier low word. Notice
that I have also replaced the separate I/O registers with a single
one which is used for both IN and OUT data. There are therefore now
10 general purpose registers available.
The idea of separating the input and output busses of the register
file is a good one. It means that the instruction decode unit
can access the output of the registers whenever it wants, without
stopping the write-back of results to the register file by
the units. Effectively then the bus arbitration circuit is
always in the result phase, which should dramatically speed
up the CPU.