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CIRCUIT DIAGRAMS: Please note that I have also made the 5 pages of circuit diagrams for this project available in a high resolution Adobe Acrobat .pdf file, which is 340kBytes big and you may find easier to read than the circuit diagrams on these pages. Click here to download.
1. Introduction
2. The Time Signal
2.1 Notes on the history of time transmission
2.2 Generation of the time data
2.3 Signal Broadcasting
2.4 Coding of the signal
3. 60 KHz Receiver
3.1 Receiver Circuit Diagram
3.2 Circuit description
3.3 Receiver tuning & adjustment
3.4 Q-Measurement
3.5 Manual Time and date decoding
3.6 Receiver section conclusion
4. Date and Time circuit
4.1 Decoder
4.2 Time and date display
4.3 Adjustment
5. Conclusion
Appendix A: Receiver testing results
Appendix B: Proposed clock extension
Appendix C: Component data
Appendix D: Photographs
References
Acknowledgements
Radio controlled clocks make use of
time signals broadcast from remote radio
transmitters, that are themselves co-ordinated
with accurate time standards, namely
caesium atomic clocks. Two such transmitters
broadcast in western Europe: These are the
DCF transmitter in Mainflingen, Germany,
on a frequency of 77.5kHz; and MSF,
Rugby, England, on 60kHz. The latter
signal in the subject of this project. The
time transmissions are encoded with
information about the time and date.
The aim of this project was to design
and build a radio receiver suitable
for picking up these signals, and to
manually decode the signals to obtain
time and date; and if sufficient time, to
construct an electronic decoder to
automatically decode and display this
information.
2.1 Notes on the history of time transmission
The first time signals were transmitted for
navigational purposes from Washington DC
in 1905 at certain times of day only. These
transmissions were at first controlled by
mechanical clocks, followed by quartz and
finally caesuim atomic clocks.
Rugby first transmitted signals in 1927,
at that time consisting of a carries wave
interrupted for 100mS every second, and
500mS every minute.
In 1974 a "fast code" was inserted
into the "minutes" break, giving time and date.
In 1978 an additional "slow code" was
added by varying the length of the "second"
break and thus giving time and date data,
spread over the whole minute. This code
will be further described later as it is
the sibject of this project.
2.2 Generation of the time data
Time data for broadcasting are based on
Caesium atomic clocks. These count the
oscillations of caesium atoms, namely
9,192,631,770 transitions between energy
states in the atom per second. Caesium
clocks currently provide the most accurate
timebase and are our ultimate standard
known as Universal Mean Time. There are
80 such clocks around the world. The
British atomic clock is the fourth most
accurate in the world, and is at the
National Physical Laboratory (NPL), Teddington,
Middlesex, England.
The time data are encoded in binary
coded decimal (BCD) and sent to Rugby,
where they are transmitted. The MSF Rugby
service is run by British Telecom International.
2.3 Signal Broadcasting
The Rugby MSF signal is broadcast at a
frequency of 60kHz with an effective
radiated power of 15kW. The transmitter
radiates sinewave signals termed carrier
waves, that are interrupted every second
in order to carry the time information.
Figure 1 shows a map of Europe with
concentric circles centered on Rugby, of
radius 700 and 900 km. Outside this range
the signal is sometimes prone to interference;
however reception is usually reliable.
Figure 2 is a graph of estimated field
strength against distance from Rugby. The
useful range is about 1500 km, but signal
reception has been reported from as far
away as Newfoundland.
The MSF Rugby signal is subject to
interruption between the hours of 10:00 and
14:00 on the first Tuesday of every month,
when the transmitter is shut down for
servicing.
2.4 Coding of the signal
The carrier wave is interrupted every
second by a break of 0.1 or 0.2 seconds
(100 / 200 ms). Time data are sent
entirely in binary form, consisting of "0"s
and "1"s. A 100 ms signal suppression
represents a binary "0", while a 200 ms
suppression represents a "1".
Figure 3 shows a schematic diagram of
the 60kHz carrier wave.
The code (slow code) starts with the
17th second of each minute. Numbers
greater than one are built up by
sending binary "one" at different seconds.
For example, referring to figure 4, the year
91 is coded by sending a "1" on the
17th, 20th, and 24th second, and a "0"
on that 18th, 19th, 21st, 22nd, and 23rd seconds.
Thus the "91" is made up of
(1*80)+(0*40)+(0*20)+(1*10)+(0*8)+(0*4)+(0*2)+
(1*1), which comes to 91.
Similarly the month, day of month, week
day (zero corrresponds to Sunday), hour,
and minute may be built up. The time
transmitted is the current civil time, ie
Greenwich mean time in winter, British Summer
time (GMT + 1 hour) in summer.
The seconds 52-59 inclusive form a
framing pattern which identifies the end of
a minute so that the clock's decoder can
lock-on to the signal. The framing pattern
is always the code 0111 1110, which is never
sent elsewhere in the coding.
In addition, "second level" data are
transmitted, consisting of a further break,
of 100 milli-seconds to indicate a "1", after
the normal, 1'st level data. This data
consists of parity checking digits that
can be used to check that the time and
date information have been received properly;
and a code called DUT 1.
This DUT 1 code arises from the fact that
the earth is an irregular timekeeper. UTC 1
and Greenwich Mean Time (GMT) are based on
a constant caesium second, not a subdivision
of the earth's rotation. DUT 1 is the difference
between UTC 1 and the time according to
the earth's rotation, so that clocks can be
corrected to earth time if necessary. The
code consists of double signal breaks
in the seconds 1-16 of each minute.
Double pulses from second 1 onwards show
DUT 1 positive, ie earth rotation ahead of MSF
Rugby, pulses second 9 onwards show DUT 1
negative. The number of such double pulses
gives DUT 1 in multiples of 100 ms. When the
DUT 1 exceeds 800 ms a second is inserted
or deleted at the 16th second in the last
minute of June or December. This is coordinated
worldwide giving Universal Coordinated Time
(UTC). This is an interesting aside but
does not concern the operation of this
project.
Figure 4 gives a complete breakdown of
the time transmission coding. For completion
I have included details of the "Fast code"
that is transmitted during the 1/2 second
break at the start of each minute.
This section describes in detail, operation and
testing of the 60kHz receiver.
3.1 Receiver Circuit Diagram
The circuit diagram of the receiver is shown
in Figure 5. The aerial used was simply a
piece of wire about 4 meters long. Coil L1
and L2 were wound from about 95 turns of
swg 30 wire on Maplin Ferrite core type 2,
LA4345. All other components are standard.
3.2 Circuit description
The 60kHz signal is selected from the range
of frequencies present at the aerial by the
L1/C2 parallel resonance circuit, which shorts
all unwanted signals of the wrong frequency,
directly to earth. TR1 forms a common emitter
amplifier which amplifies the signal and further
reduces signals outside the required range with
the L2/C7 tuned circuit in its collector load.
TR2 and TR3 and their associated components
further amplify the signal until at point A in
the circuit, the waveforms look like in
Figure 6.
Next, D1 & C13, together with R15, C14, R16
as a low-pass filter, demodulate the signal,
giving a voltage whose RC component is a
measure of the signal amplitude. This is shown
in Figure 7, as the voltage at point B.
Ideally the waveform would be like the dotted
line, if it were not for interference and background
noise.
The signal now passes through the unity gain
operational amplifier circuit of IC1, which
buffers the signal so that the following signal
processing stages do not place undue load
on the preceeding filter.
Capacitor C15 changes up to the maximum
level of the signal, while capacitor C16 changes
to the minimum signal level. Variable resistor
VR1 selects a value somewhere between these extremes.
IC2 is configured as a comparator,
which gives a positive output where the voltage
at B is less than the "mean" level from VR1,
and a negative output if it is greater. D4,
D5, and R17 clip this signal so that it will
always remain in the range -0.6 to 5.6 volts,
and therefore not damage the input of
IC3. All these signals are shown in Figure
8a / b.
Integrated circuit IC3 contains six Schmitt
trigger inverters. The operation of these is as
follows. On the transition from a low to high
voltage, the input must reach 1.7V in order
to give an inverted (ie low) output. However,
on the following high to low transition, the
input must fall to a lower voltage, 0.9V
in order for the inverted to change state. This
device has many uses, including as a remover
of transient voltages.
In the receiver circuit, the output of IC2
may contain spurious pulses near the transition
due to the "messy" nature of the signal B. IC3f
invertes the signal G, and this passes into
a resistor/capacitor network, R18, C17, & R19,
which together with IC3e, remove any transient
pulses which may be present. The voltage
across the capacitor C17 (point H) follows
the output of IC3f, but as it charges
through R18 and discharges through R19, the
voltage at H is slightly slow to respond to
the output of IC3f. Due to the important
property of schmitt triggers, the inverter
IC3e does not respond to the transients,
and they are thus removed from the final
signal, I, which gives a clean pulse in
time with the Rugby MSF transmissions.
LED D7 flashes in response to the transmission.
The voltages associated with this "signal cleaning"
circuit are shown in Figure 9.
This circuit delays the pulse slightly and
means that the length is not exactly 100 or 200
milliseconds, but in practice this is not
important.
3.3 Receiver tuning & adjustment
An oscilloscope was connected across C10,
with both coils wound with about 105 turns.
First L1 and then L2 were tuned by removing
one turn at a time until the signal on the
CR0 screen was of maximum amplitude. Then
VC1 was adjusted to give maximum amplitude
also; VC1 was at its middle position while L1/L2
adjustment took place.
A voltmeter was placed across C14 and VR2
adjusted to give reasonable swing between
high and low voltages.
Figure 9: Voltage associated with signal cleaning.
VR1 was adjusted to give a clean output
pulse at I. This adjustment was found not to
be critical.
3.4 Q-Measurement
The Q of a tuned system such as a radio
receiver is a measure of its selectivity, that
is, its ability to respond to one particular
frequency and reject others close to the
designed frequency. The higher the Q, the
better the selectivity. To find the Q, it is
necessary to first plot a receiver response
curve.
This was done using a signal generator
attatched to a frequency counter and a
piece of wire approximately one metre in
length. The receiver aerial was about one
metre in length also and placed near the
first wire. The output peak to peak voltage,
measured across C10, was plotted against
frequency in the range 0-100 kHz. The
measurements are listed in Appendix A,
and the response curve is shown in figure
10.
The Q is given by center frequency divided
by response width, where this width is taken
at half the height.
The Q of this receiver is 11.5. This is quite
high for such a simple receiver and in certainly
adequate for reception of the Rugby MSF signal.
3.5 Manual Time and date decoding
A chart recording of the receiver output
at point B, i.e. across capacitor C14, and
is shown in figure 11. The chart recording
was decoded by hand using the time
code format of Figure 4. The code was
decoded on Thuseday 14 March 1991 at 16:53.
3.6 Receiver section conclusion
This completes the receiver design, construction,
tuning, and manual decoding, and thus
complete the necessary project requirements.
This section describes in detail the circuit that
was designed and built to decode and display
time and date automatically.
4.1 Decoder
The decoder circuit diagram is shown in figure 12.
Capacitor C18 begins to change through VR3
at the start of each pulse from the receiver.
After about 015seconds the voltage acrosee the
capacitor is sufficient to trigger the input of
IC3c and cause its output to go low. This
will only happen during 200 ms pulse, ie "1"s,
as the 100 ms pulse does not allow C18 to
charge to a high enough voltage to cause
IC3c to charge state. Thus the output of
IC3c at the end of each 100/200 ms pulse
is low for a "1" and high for a "0".
IC4d inverts the receiver pulse so that on
its falling edge, the data from the output
of IC3c is clocked into a D-type flip-flop,
IC5a. IC5a-h are connected as an 8-bit
shift register. On the positive going edge of
each clocking pulse, the data at the D-input
of each flip-flop is latched and transferred
to the Q-output. Thus at each clock pulse,
the data is shifted along the shift register one
place. IC's 7, 8, 9 and 10 continue this chain
so that each second, data enters the next
flip-flop, IC5a, and on the next second, is
shifted along to make room for the next
digit, etc. By the 59th second, all the
information necessary to decode time and
date is resident in the shift register. The
Q16-Q51 labelled outputs indicate the data
at that output is the valid data received at
the numbered second, when the 59th second
has been detected.
The 59th second is detected by IC6, an 8-
input NAND gate, whose output goes low
only when the code 0111 1110 is present in the
first eight flip-flops, ie the end of minute
identifier is present.
This signal clocks flip-flops IC12a/b, which
initially contain "0"s. The flip-flops are
configured as a two-bit shift register, with
the first D-input connected to "1". After two
minute identifier pulses, i.e. after a whole
minute of data has been received, this
"1" gets through to the output, and the
signal "RUGBY" goes high, indicating that the
shift registers contain valid data and the
clock is synchronised to RUGBY MSF. Now the
output of NAND gate IC14 goes low, and data
may be clocked into the time and date circuits
described in the next section. Also, AND gate
IC13a and OR gate IC15b allow seconds pulses
to reach the seconds counter of that circuit.
Capacitors C20 and C21 are changed every
time a seconds pulse occurs. They slowly
discharge during the gaps between pulses,
and if a pulse does not occur, due to
poor signal reception for instance, the capacitors
discharge to a low enough level to allow
ICs 3a and 4a to charge state, causing flip-
flops IC12a and b to be cleared; the RUGBY signal
now goes low and another whole minute must
be received before the clock synchronises to
Rugby time again.
These signals are all shown in Figure 13.
Note that the circuit around IC4b, IC4c, C19, and
VR4 removes the second pulse that is received
near the start of each minute, so that no double
pulses are allowed to clock the seconds counter.
4.2 Time and date display
The time and date display circuit diagram is fig 14.
When the /PR signal is low, indicating valid
data, the next seconds pulse loads the six
presetable binary counters, IC22-27, with
the valid time information and PR loads the
date registers, IC31 and IC32 & IC33, with the
valid date information.
Six presetable binary counters are used to
store the time. The first two IC26 and 27,
count seconds pulses for the seconds display-
IC22, 23, 24, 25 need not have been counters,
since in this circuit they are just used to store
the data; however, a planned extension to
this project is to make a backup circuit
so that the clock may still operate in times
of transmitter shut-down or exceptionally
poor reception. This is further discussed in
Appendix B. These counters are binary
counters thus some external logic is required
to make them count to 60 properly. The
NAND gate at the outputs of IC27 detects the
"10" condition and immediately resets the
counter. The NAND at the outputs of IC26 detects
"60" and similarly returns the counter to zero.
Similar NAND gates at the outputs of the other
counters (IC34a-d) are connected in preparation for the circuit in Appendix B.
The outputs of the six counters pass to
the inputs of three latches, IC28-30, which
are not used as latches here, but are
connected so that the outputs follow the
inputs. Each integrated circuit contains eight
latches. A common enable input sets the
outputs into a "high impedance" state when
it is high.
IC31-3 are each 8 D-type flip-flips, as used in
the decoder, Figure 14. They store the date and
their outputs are also controlled by an
enable input, which must be low, ie "0",
for data to be output. These outputs and
the outputs of the time latches, IC28-30,
are both cannected to the display drivers,
IC16-21. Both sets of outputs may be connected
together, so long as both sets are not
enabled at the same time, causing a
conflict to occur.
IC36a, b, IC37b ensure that no conflict
can occur. At switch-on the flip-flop
IC36b is preset to a "1", and the other
flip-flop are reset, by C23 and R24.
Initially, the voltage across C23 is zero, causing
the necessary setting og the flip-flops, before
R24 causes C23 to change up. Thus at
switch-on the time enable output is low and
the time latches, IC28-30 output their data;
While the date enable output is high, so
no conflict can occur.
When clocked, the "001" data in the
flip-flops is rotated so that date is displayed
instead. The clocking is accomplished using
the circuit around IC38f, C22, R26, S1. Pushing
the button causes the flip-flops to be clocked.
R25, C22, and IC38f prevent spurious pulses
caused by dirty switch contact, which
always occur, from reaching the flip-flops.
The operation of this part of the circuit is
shown in figure 15.
IC's 16-21 are binary to 7-segment display
drivers. They convert binary data at their
inputs into a form suitable for driving
the 7-segment displays which are connected
to their Outputs. 7-segment displays are the
displays that form numbers by selectively
lighting seven segments arranged in an eight;
they are familiar in calulators and digital
watches. Such LED's must be connected
in series with 220 ohm resisters in this application,
to prevent too high voltages from damaging
them. (R33-74)
R27, D11, D12 cause the 10-hours digit to be
blanked, by putting IC16's /RB1 input low,
if this digit is a zero. Thus at 8 hours, 8
is displayed, not 08.
R28,R29,D13 and D14 provide a similar service,
blanking the 10 months display, only while the
date display it operative, if this digit is a zero.
IC20 is blanked during alarm display
(see appendix B).
Note that 0.1uF decoupling capacitors
are necessary across the supply of the TTL
chips in order to ensure their correct operation
and stability.
4.3 Adjustment
Adjustment of the two variable resistors in
the decodes circuit, figure 12, must be
accomplished before circuit operation is
possible. An LED was connected in series
with a 220 ohm resistor to earth at the
point M in figure 12. VR3 was adjusted
until the LED was lit in the second
immediately following a long 200m s pulse,
ie a "1", and not lit after a short, 100ms
pulse (a "0"). After this adjustment,
the clock synchronised to MSF Rugby time
within two minutes of switch-on. Now VR4
was adjusted so that the seconds counted
properly each second, and not twice during
the double pulses of the DUT 1 code at
the start of each minute.
This completed adjustment of the
clock and normal operation was possible at
last.
This project was successful in building
a receiver to pick up the Rugby Time signals,
and a decode and display circuit to show
time and date selectable at the push of a
button. An alarm circuit, power supply, and
backup circuit are described in Appendix B.
This planned extension of the project is
under construction and has so far been
successful. It is hoped that after its completion
the unit will be encased in a smart
box, and function permanently as a
domestic alarm clock, self setting and ever
accurate.
This project has been extremely interesting
and enjoyable to complete.
Signal generation output = 2.00V peak to peak.
Measurements (see table, right) were taken using a frequency
counter to measure the signal generator frequency;
a one-metre piece of wire at the signal
generator output, placed near a 1 metre piece of
wire used as an aerial for the receiver. The
data are referred to in section 3.4 of this
report and plotted on a graph in fugure 10.
This circuit, figure 16, contains on alarm,
power supply, and backup. The two 74LS593
binary counters are set by the two buttons,
"SLOW" and "FAST", when the alarm is being
displayed, ie Alarm /OE is low. The counters
outputs pass through two octal D-type
latches whose outputs are only enabled when
Alarm /OE is low.
The counter outputs are compared to the time
outputs using a set of XOR-gates, whose
outputs are only low if the two inputs are
equal. When hours and minutes are
equal a type 74LS74 flip-flop is set, and
when minutes but not hours are equal, the
flip-flop is reset. The output of this flip-flop
enables an audio-frequency oscillator, which
drives a telephone loudspeaker, through a transistor
buffer. The oscillator is disabled periodically
by another oscillator, which pulses several
times a second, thus giving the alarm a bleeping
sound. The alarm sounds for 1 hour.
A 12-0-12 V transformer, 3-bridge rectifiers,
and a 5V voltage regulator, provide +/-12V
power supplies for the op-amps in the receiver.
and 5V Vcc for the TTL chip's power supplies.
Another 74LS393 dual binary counter divides
the 50Hz mains frequency to give one pulse
per second. This is used to drive the clock in the
event of signal loss. When the Rugby signal is
lost, the clock automatically switches over to
this back up, and carries on telling correct time.
The TTL Data Book for Design Engineers, 2nd edition.
An article from Wireless World. July 1978, P66.
An article from practical Electronics, March 1990, P15.
Radio Time Magazine, Autumn 1990.
Thanks to the project supervisor Roy Taylor
of the Laser Physics Group, and also to the
lab. staff who were all most helpful.
