After enjoying the Simple man's Spectrum Analyser so much, here's some real insanity. The Mk2 spectrum analyser is an attempt to resolve some of the shortcomings of the original simple analyser, improve performance, and add hosts of features. The display uses an ex-TV tube, with digital storage. Purely for the fun of it, the digital circuits are built using discrete logic rather than a microprocessor.
The new analyser has the following target feature list (some of which may or may not be attained):
o Frequency coverage 0 to 1000 MHz o 95dB dynamic range o Built in tracking generator o Selectable resolution filters o Selectable sweep speeds (very slow sweeps possible) o Digital storage, up to 8 storage channels o Dual channel CRT display o Ability to display addition or subtraction of 2 channels o Frequency measurement with on-screen digital display o Amplitude measurement with on-screen digital display o Computer interface to PC parallel port for screen dumps
The original thoughts on the new analyser were written in this .pdf document. Since then I decided to greatly simplify front panel layout and make a neater display by using the CRT itself for digital frequency and amplitude readout rather than separate 7-segment LED displays. Most of the rest of that document remains valid, although several new features have been added later.
The display format uses the standard European PAL timing, i.e. 50 frames per second and 625-line interlaced (15625 Hz horizontal frequency). I use the central 40uS section of the 64uS horizontal scan line, divided into 320 pixels. The analyser trace therefore occupies 320 x 256 pixels of display area. Below that 16 scan lines will be used as a 320 x 16 pixel block for textual display, comprising 2 rows of 40 characters. That's plenty of space to display frequency and amplitude information, as well as other settings e.g. db/div, sweep rate etc.
The character generator uses a 128KByte FLASH chip. A completely excessive storage capability considering that minimalistically an 8 x 8 pixel grid would require only 80 bytes for the digits 0-9 (but more would be nice for text capability). However FLASH is considerably cheaper than EEPROM, so the cheapest available chip is used. In practice the large size results in other simplifications, since a different character map can be used for each of the 80 displayed characters, therefore text settings information can be displayed easily by selection of only one or two digital address lines.
This project is still under construction and likely to take a long time. Below are some brief details on the design, and pictures of progress to date (click the pictures for bigger versions). The screenshots from the new digitised display are at the bottom of this page.
We start with a small black and white TV/clock/Radio. This was bought at a car boot sale a few years ago, sold as defective with no picture just a horizontal line. I correctly suspected a fault in the vertical deflection circuit, replaced a transistor in the vertical deflection amplifier, and the TV worked perfectly.
Here's the result of my TV conversion to a miniature 4.5-inch diagonal computer monitor taking TTL-level video and composite sync inputs. To get to this stage I carefully traced the PCB tracks and drew the TV circuit diagram, dismantled it, then rebuilt the PSU, high-voltage and deflection driver sections onto perf board. The tube is mounted (for now) on a sheet of unetched PCB. The voltage stabiliser transistor is on the heatsink at the back. New driver board is mounted on a vertical PCB wall to the right of the TV tube.
Pictured left you can see the sync separator and deflection oscillator board. This uses the AN5151 chip from the original TV. The KA2915 is equivalent to the AN5151, click here for datasheet. On the right here's the remainder of the TV's circuit board after all the important TV sections were removed.Click here for the circuit diagram of my monitor conversion, and the digital timing generator (pdf format).
The digital sections of the analyser are built on 3 (currently) circuit boards sized 6 by 4 inches (15 x 10 cm). They plug into a backplane using 64-way connectors from my junk box. The backplane also temporarily accomodates an op-amp circuit used for conversion of analogue input and output to the Simple man's Spectrum Analyser, together with an 8-way DIP switch functioning temporarily as a "front panel", for selection of storage modes etc.
The first board built is the middle one in the above assembly. It contains the timing generator (all timing is derived from a 16MHz crystal), row and column counters, and storage memory. The memory is an 8K SRAM chip (bottom right of photo). Each analyser sweep consists of 640 8-bit measurements. There is therefore plenty of space in the 8K memory for 8 channels. My usual construction techniques use point to point wiring and plain (no copper tracks) matrix board.
The analogue board (left) contains a 10-bit digital to analogue converter (DAC) which generates the sawtooth for the VCO sweep. A 10-bit analogue to digital converter (ADC) digitises the analyser's logarithmic output for storage (most significant 8 bits) in the memory. The comparator board (right) contains the interpolator, and character ROM for the text output (on-screen frequency/amplitude readout). Only the rightermost 11 chips on this board are currently wired.
Nightmare alert! Unknown to me in advance, the ADC chip (left) turned out to be a tiny surface mount 24-pin TSSOP package. Pin spacing a mere 0.65mm (0.0256 inches). Mounting it took 4 hours, much PCB trace scratching with a knife, and soldering hair-thin copper strands from ordinary stranded wire. The DAC was easy in comparison (see right). Both modules are mounted in small PCB boxes bolted to the board.
Test setup. At present I am using the existing Mk1 Analyser as the RF section. The ADC and DAC circuits both use the voltage range 0 - 2.5V so some voltage conversion is necessary. I fitted a socket to the back of the existing analyser to allow external sweep input. I have a +9V and -9V supplies from the TV PSU, an op-amp on the backplane multiplies the sawtooth by about 3 before feeding it to the analyser VCO. Since the internal ramp generator in the analyser uses 0 - 12V the sweep range isn't as wide using this test setup, but it's sufficient for testing.
The logarithmic Y output still feeds the oscilloscope (left), but now also the ADC. Notice the beaded appearance of the 'scope display, this is due to the VCO sweep now being in reality a "staircase" ramp with 640 discrete levels, rather than a real continuous sawtooth. Shown here, 10MHz crystal calibrator with 2nd and 3rd harmonics. Right: The digitised display on the new monitor, again the 10MHz calibrator with sweep approx 2 - 42 MHz.
Here I proudly show off the digitally generated 10 by 8 graticule (left). Further attention to the video driver circuit is required to correct graticule fading at the top. I would also like to decrease the graticule brightness further relative to the main trace. Right: dual channel mode will look like this (currently both channels are the same). I'll probably arrange for the graticule to automatically adjust to twice the number of vertical divisions in 2 channel mode.
Here's the 2-channel mode with the graticule switched off (one of the DIP switches controls the graticule, another selects 1 or 2 channel display). Right: a closeup of the noisefloor, obtained by adjusting the op-amp input scaler. Such adjustments will be digitally selectable when I'm finished, with db/div displayed. Some stretching of the image indicates again that some modifications to the video driver are needed. Such harsh black and white contrast is very different to the usual gentle TV picture for which the circuit was originally designed.
Up close and personal with a narrow sweep of the 10MHz crystal calibration oscillator. This shows the filter shape of the analyser, as well as the clarity of the new digital display. Right: Box of chips. The large 32-pin DIP is a 128K FLASH memory which will form the character generator ROM for the on-screen frequency and amplitude display.